Ventus RISC-V GPGPU isa simulator based on Spike.
This simulator is developed by 张泰然 and 郑名宸.
This simulator adds the following features into origin spike simulator:
For more information of the original Spike, please refer to README-spike-origin.md
see document in https://github.com/THU-DSP-LAB/riscv-gnu-toolchain/tree/main/rvv-gpgpu/documents
Build step is identical to the origin build step of Spike. Assume that the RISCV enironment variable is set to the RISC-V tools install path.
$ apt-get install device-tree-compiler
$ mkdir build
$ cd build
$ ../configure --prefix=$RISCV
$ make
$ [sudo] make install
We execute Ventus GPGPU program with Spike in machine mode. To produce executable file, we utilize libgloss-htif and the modifed version of riscv-gnu-toolchain. The following commands set the necessory environment.
# install riscv64-unknown-elf toolchain
$ git clone https://github.com/THU-DSP-LAB/riscv-gnu-toolchain.git
$ cd riscv-gnu-toolchain
$ mkdir build && cd build
$ ../configure --prefix=$RISCV --with-isa=rv64gv --with-abi=lp64d --with-cmodel=medany
$ make
# install libgloss-htif
$ cd ..
$ git clone https://github.com/ucb-bar/libgloss-htif.git
$ cd ligbloss-htif
$ mkdir build && cd build
$ ../configure --prefix=${RISCV}/riscv64-unknown-elf --host=riscv64-unknown-elf
$ make
$ make install
For futher reference, pleace refer to the corresponding instructions provided by libgloss-htif and riscv64-gnu-toolchain
Assuming assembly code test.s, we use following commands.
$ riscv64-unknown-elf-gcc -fno-common -fno-builtin-printf -specs=htif_nano.specs -Wl,--defsym=__main=main -c test.s
$ riscv64-unknown-elf-gcc -static -specs=htif_nano.specs -Wl,--defsym=__main=main test.o -o test.riscv
And use Spike to execute test.riscv.
$ spike -d -p4 --isa=rv64gv --varch=vlen:256,elen:32 --gpgpuarch numw:4,numt:8 test.riscv
We add gpgpuarch option to configure uArch parameters for Ventus GPGPU (numw to set total warp number and numt to set thread number per warp). Note that there are some constraints about the parameters:
For more spike options, use spike -h
GPGPU execution is different from conventional CPU with vector extension in two aspect:
We implement software models of simt stack and warp scheduling to support above features, and add enhanced interactive mode commands to display simt stack and warp scheduling information.
command | usage | function |
---|---|---|
simt-stack | simt-stack <core> | Display simt stack info given hartid |
warp-barrier | warp-barrier | Display global warp barrier info(numw, numt and barrier bit vector) |
mem-region | mem-region <hex addr> <hex size> | Show contents of physical memory given base memory and size |
For more interactive mode commands, use help
in interactive mode.
In this section, we will introduce how to programm programs with Ventus GPGPU extension that can run in Spike. Since the software stack is not mature, this section may be changed a lot in the future.
First, we introduce how to program branch and loop with custom instructions.
Psuedo code for branch is shown as below.
# if(condition(for example: vs1 == vs2))
# ture_branch_code;
# else
# false_branch_code;
BRANCH:
vbne vs1, vs2, FALSE_BRANCH
true_branch_assembly_code
join v0, v0, BRANCH_JOIN
FALSE_BRANCH:
false_branch_assenbly_code
join v0, v0, BRANCH_JOIN
BRANCH_JOIN:
end_of_the_branch
Psuedo code for loop is shown as below.
vblt v0, v1, LOOP
join v0, v0, LOOP_END
LOOP:
loop_body
join v0, v0, LOOP_COND_EVAL
LOOP_COND_EVAL:
vblt v0, v1, LOOP
join v0, v0, LOOP_END
Since we use libgloss-htif to produce machine mode executable, extra codes are needed.
main:
addi sp,sp,-16
sd s0,8(sp)
addi s0,sp,16
j start_of_your_program
main_end:
li a5,0
mv a0,a5
ld s0,8(sp)
addi sp,sp,16
ret
start_of_your_program:
...
j main_end
In future version, we may develop custom linker scripts to replace libgloss-htif and the extra codes will be unnecessary.
Current version needs the assembly program to obey following conventions to be executed sucessfully in Spike. Some of them may be changed in future version.
We provided testcased in path gpgpu-testcase. To run the testcase, change directory to gpgpu-testcase and execute makefile script.
compile the testcase $ make TEST=[testcasename]
invoke spike to run the testcase $ make spike-sim TEST=[testcasename]
PS:
We provide the following testcases
name | function |
---|---|
branch-basic | test for simple branch |
branch-nested | test for nested branch |
loop | test for loop |
barrier | test for inter warp barrier |
gaussian | gaussian testcase |
saxpy | saxpy testcase implemented with extended gpgpu instructions |
saxpy2 | saxpy testcase implemented with conventional rvv instructions |
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