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FiberCOMM / PSTR17R5B

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PSTR17R5B.gise 1.48 KB
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FiberCOMM 提交于 2020-10-21 15:48 . 1.增益控制改为DS3502芯片
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="PSTR17R5B.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_SYNPLIFY_MISC" xil_pn:name="top.sdc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1592740040" xil_pn:in_ck="3400848023675725975" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1592740040">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
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