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WayneGong 提交于 2019-11-24 12:01 . Initial commit
(_flow fab_demo "2019.1-patch11"
(_comment "Generated by Fabric Compiler (version on 2019.1-patch11<build 44256>) at Sun Nov 24 02:03:19 2019")
(_version "1.0.1")
(_status "initial")
(_project
(_option prj_work_dir (_string "."))
(_option prj_impl_dir (_string "."))
)
(_task tsk_setup
(_widget wgt_select_arch
(_input
(_part
(_family Logos)
(_device PGL22G)
(_speedgrade -6)
(_package BG324)
)
)
)
(_widget wgt_my_design_src
(_input
(_file "source/coor_trans/hdl/coor_trans.v"
(_format verilog)
(_timespec "2019-11-21T20:39:30")
)
(_file "source/coor_trans/hdl/coor_trans_forward.v"
(_format verilog)
(_timespec "2019-11-21T18:24:23")
)
(_file "source/coor_trans/hdl/coor_trans_reverse.v"
(_format verilog)
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)
(_file "source/coor_trans/hdl/cos_table.v"
(_format verilog)
(_timespec "2019-11-22T10:49:57")
)
(_file "source/coor_trans/hdl/sin_table.v"
(_format verilog)
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)
(_file "source/ddr3/ddr3.v"
(_format verilog)
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)
(_file "source/ddr3/rtl/ipsl_ddrc_apb_reset.v"
(_format verilog)
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)
(_file "source/ddr3/rtl/ipsl_ddrc_reset_ctrl.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/ipsl_ddrphy_dll_update_ctrl.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/ipsl_ddrphy_reset_ctrl.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/ipsl_ddrphy_training_ctrl.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/ipsl_ddrphy_update_ctrl.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/ipsl_hmemc_ddrc_top.v"
(_format verilog)
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)
(_file "source/ddr3/rtl/ipsl_hmemc_phy_top.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/ipsl_phy_io.v"
(_format verilog)
(_timespec "2019-05-05T16:18:21")
)
(_file "source/ddr3/rtl/pll/pll_50_400.v"
(_format verilog)
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)
(_file "source/display_module/char_array_decode.v"
(_format verilog)
(_timespec "2019-06-22T00:31:34")
)
(_file "source/display_module/Char_Pic_Disply.v"
(_format verilog)
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)
(_file "source/display_module/char2_array_decode.v"
(_format verilog)
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)
(_file "source/display_module/RGB_Gary_Binary.v"
(_format verilog)
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)
(_file "source/display_module/timing_gen_xy.v"
(_format verilog)
(_timespec "2019-11-07T01:48:54")
)
(_file "source/display_module/video_timing_data.v"
(_format verilog)
(_timespec "2019-11-02T21:42:19")
)
(_file "source/dvi_tx/dvi_encoder.v"
(_format verilog)
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)
(_file "source/dvi_tx/encode.v"
(_format verilog)
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)
(_file "source/dvi_tx/serdes_4b_10to1.v"
(_format verilog)
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)
(_file "source/i2c_master/i2c_config.v"
(_format verilog)
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(_file "source/i2c_master/i2c_master_bit_ctrl.v"
(_format verilog)
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)
(_file "source/i2c_master/i2c_master_byte_ctrl.v"
(_format verilog)
(_timespec "2017-07-25T12:32:56")
)
(_file "source/i2c_master/i2c_master_defines.v"
(_format verilog)
(_timespec "2017-07-25T12:32:56")
)
(_file "source/i2c_master/i2c_master_top.v"
(_format verilog)
(_timespec "2017-07-25T12:32:56")
)
(_file "source/sources_1/aq_axi_master.v"
(_format verilog)
(_timespec "2018-03-01T10:16:58")
)
(_file "source/sources_1/cmos_8_16bit.v"
(_format verilog)
(_timespec "2019-11-09T17:12:44")
)
(_file "source/sources_1/cmos_write_req_gen.v"
(_format verilog)
(_timespec "2019-11-09T17:13:59")
)
(_file "source/sources_1/frame_fifo_read.v"
(_format verilog)
(_timespec "2018-01-10T16:36:17")
)
(_file "source/sources_1/frame_fifo_write.v"
(_format verilog)
(_timespec "2017-07-25T12:32:56")
)
(_file "source/sources_1/frame_read_write.v"
(_format verilog)
(_timespec "2019-11-21T14:57:18")
)
(_file "source/sources_1/Key_Module.v"
(_format verilog)
(_timespec "2019-10-05T00:02:37")
)
(_file "source/sources_1/lut_ov5640_rgb565_1024_768.v"
(_format verilog)
(_timespec "2017-07-25T12:32:48")
)
(_file "source/sources_1/top.v" + "top"
(_format verilog)
(_timespec "2019-11-22T22:30:36")
)
(_file "source/display_module/color_bar.v"
(_format verilog)
(_timespec "2017-07-25T12:32:56")
)
(_file "source/display_module/video_define.v"
(_format verilog)
(_timespec "2018-01-11T16:43:20")
)
(_file "source/sources_1/image_processing.v"
(_format verilog)
(_timespec "2019-11-22T22:45:29")
)
)
)
(_widget wgt_my_ips_src
(_input
(_ip "ipcore/afifo_16i_16o_512/inst.idf"
(_timespec "2019-11-21T13:55:46")
(_ip_source_item "ipcore/afifo_16i_16o_512/rtl/ipml_fifo_ctrl_v1_3.v"
(_timespec "2019-06-17T17:36:48")
)
(_ip_source_item "ipcore/afifo_16i_16o_512/rtl/ipml_sdpram_v1_4_afifo_16i_16o_512.v"
(_timespec "2019-11-21T13:55:46")
)
(_ip_source_item "ipcore/afifo_16i_16o_512/rtl/ipml_fifo_v1_4_afifo_16i_16o_512.v"
(_timespec "2019-11-21T13:55:46")
)
(_ip_source_item "ipcore/afifo_16i_16o_512/afifo_16i_16o_512.v"
(_timespec "2019-11-21T13:55:46")
)
)
(_ip "ipcore/video_pll/inst.idf"
(_timespec "2019-05-07T18:16:43")
(_ip_source_item "ipcore/video_pll/video_pll.v"
(_timespec "2019-05-07T18:16:43")
)
)
(_ip "ipcore/osd_rom/inst.idf"
(_timespec "2019-11-22T18:48:40")
(_ip_source_item "ipcore/osd_rom/rtl/ipml_rom_v1_3_osd_rom.v"
(_timespec "2019-11-22T18:48:40")
)
(_ip_source_item "ipcore/osd_rom/rtl/ipml_spram_v1_3_osd_rom.v"
(_timespec "2019-11-22T18:48:40")
)
(_ip_source_item "ipcore/osd_rom/osd_rom.v"
(_timespec "2019-11-22T18:48:40")
)
)
)
)
(_widget wgt_import_logic_con_file
(_input
(_file "source/Image_Rotate.fdc"
(_format fdc)
(_timespec "2019-11-01T15:52:39")
)
)
)
(_widget wgt_edit_user_cons
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_simulation
)
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 0))
)
(_widget wgt_rtl_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 4))
(_option synplify_pro (_switch ON))
(_option selected_syn_tool_opt (_integer 1))
(_output
(_file "synthesize/stdout.log"
(_format text)
(_timespec "2019-11-22T22:47:44")
)
(_file "synthesize/synlog.tcl"
(_format text)
(_timespec "2019-11-22T22:47:44")
)
(_file "synthesize/top.vm"
(_format verilog)
(_timespec "2019-11-22T22:47:33")
)
(_file "synthesize/synplify.scf"
(_format sdc)
(_timespec "2019-11-22T22:47:35")
)
(_file "synthesize/synplify.lcf"
(_format lcf)
(_timespec "2019-11-22T22:47:34")
)
(_file "synthesize/synplify.log"
(_format text)
(_timespec "2019-11-22T22:47:47")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2019-11-22T22:47:48")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_my_fic_src
)
(_widget wgt_inserter_gui_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 4))
(_db_output
(_file "device_map/top_map.adf"
(_format adif)
(_timespec "2019-11-22T22:47:55")
)
)
(_output
(_file "device_map/top.dmr"
(_format text)
(_timespec "2019-11-22T22:47:55")
)
(_file "device_map/top_dmr.prt"
(_format text)
(_timespec "2019-11-22T22:47:52")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2019-11-22T22:47:55")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/top.pcf"
(_format pcf)
(_timespec "2019-11-22T22:47:55")
)
)
)
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 4))
(_db_output
(_file "place_route/top_pnr.adf"
(_format adif)
(_timespec "2019-11-22T22:48:44")
)
)
(_output
(_file "place_route/top.prr"
(_format text)
(_timespec "2019-11-22T22:48:44")
)
(_file "place_route/top_prr.prt"
(_format text)
(_timespec "2019-11-22T22:48:43")
)
(_file "place_route/top_plc.adf"
(_format adif)
(_timespec "2019-11-22T22:48:24")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2019-11-22T22:48:46")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_timing_analysis
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 4))
(_attribute _auto_exe_lock (_switch OFF))
(_option input_pins (_boolean FALSE))
(_db_output
(_file "report_timing/top_rtp.adf"
(_format adif)
(_timespec "2019-11-22T22:48:57")
)
)
(_output
(_file "report_timing/top.rtr"
(_format text)
(_timespec "2019-11-22T22:48:57")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2019-11-22T22:48:58")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_power
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_command cmd_gen_netlist
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
(_option sdf_annotate (_boolean FALSE))
)
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 4))
(_output
(_file "generate_bitstream/top.sbit"
(_format text)
(_timespec "2019-11-22T22:49:28")
)
(_file "generate_bitstream/top.smsk"
(_format text)
(_timespec "2019-11-22T22:49:28")
)
(_file "generate_bitstream/top.bgr"
(_format text)
(_timespec "2019-11-22T22:49:28")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2019-11-22T22:49:28")
)
)
)
)
)
Verilog
1
https://gitee.com/gongwenhong/Image_Rotate.git
git@gitee.com:gongwenhong/Image_Rotate.git
gongwenhong
Image_Rotate
Image_Rotate
master

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